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Morphing Machines raises $2.76M in a seed round led by Speciale Invest and supported by IvyCap Ventures, Golden Sparrow, Navam Capital, CIIE Initiatives, and DeVC to develop REDEFINE, a many-core processor Soft IP.

Morphing Machines raises $2.76M in a seed round led by Speciale Invest and supported by IvyCap Ventures, Golden Sparrow, Navam Capital, CIIE Initiatives, and DeVC to develop REDEFINE, a many-core processor Soft IP.

06/26/24, 7:05 AM
Location
https://purecatamphetamine.github.io/country-flag-icons/3x2/IN.svgbangalore
Money raised
$2.76 million
Industry
manufacturing
Round Type
seed
Investors
De Vc, Ciie Initiatives, Navam Capital, Golden Sparrow, Ivy Cap Ventures, Speciale Invest
Fabless semiconductor startup Morphing Machines has secured $2.76 million in its seed round, which was led by Speciale Invest and supported by IvyCap Ventures, Golden Sparrow, Navam Capital, CIIE Initiatives, and DeVC. The funding will be used to ramp up product development, expand the engineering team, and support go-to-market initiatives.

Company Info

Company
Morphing Machines
Location
bangalore, karnataka, india
Additional Info
Morphing Machines Pvt Ltd is a closely held fabless semiconductor company based in Bangalore. Morphing Machines was launched from the Technology Entrepreneurship Initiative of the Indian Institute of Science at Bangalore. The patented REDEFINE™ technology from Morphing Machines is a path-breaking new SoC architecture and platform for implementing run-time reconfigurable silicon cores for massively parallel and heterogeneous many-core processors. A single REDEFINE™ based application core accelerates an entire class of related applications while optimizing space and power usage. REDEFINE™ enables ASIC-like high performance at an affordable NRE cost for a much wider range of compute-intensive applications than has ever been possible before. The REDEFINE™ Meta Compiler framework enables targeting application implementations to a REDEFINE™ application core through automatic concurrency analysis and generation of hardware reconfiguration meta-data, supported by cycle-accurate REDEFINE™ Simulators for pre-synthesis design validation.

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